Chip testing circuit and testing method thereof
US11287466B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Oct 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/69
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A chip testing circuit and a testing method thereof are provided. The chip testing circuit includes a parameter measurement circuit, a plurality of power supply circuits, a plurality of switch circuits, and a control circuit. The plurality of power supply circuits respectively provide power supply to a plurality of chips carried by a plurality of sockets. Each switch circuit is electrically connected between one socket and one power supply circuit. The control circuit is connected in parallel to a plurality of signal pins of the plurality of chips carried by the plurality of sockets, so that when the control circuit outputs test data, all the chips can simultaneously receive the test data. When executing a parametric test mode, the control circuit controls one of the switch circuits to be turned on and controls the parameter measurement circuit to perform an electrical performance test on the chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.