Integrated circuit design modification for localization of scan chain defects
US11288428B1 · kind B1 · utility
3Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 30, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Oct 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/02
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit (IC) design comprising a scan chain may be received, where stimulus values may be scanned-in and response values may be scanned-out through a scan path in the scan chain, where the scan path may include a first scan cell and a second scan cell such that the first scan cell is downstream with respect to the second scan cell. The scan chain may be modified to enable observation of a 0 and a 1 value in the first scan cell in presence of a defect in the second scan cell, or observation of a 0 and a 1 value in the second scan cell in presence of a defect in the first scan cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.