Patent · US Active

Computer implemented system and method for generating a layout of a cell defining a circuit component

US11288432B2 · kind B2 · utility

4Cited by

9References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Andy Wangkun Chen · Austin, US
Yew Keong Chong · Austin, US
Tom Shore · Austin, US
Gus Yeung · Austin, US
Marlin Wayne Frederick, Jr. · Austin, US
Sriram Thyagarajan · Austin, US

Key dates

Filing date	Oct 3, 2020
Grant date	Mar 29, 2022
Priority date	—
Expiry date	Oct 3, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F2111/04
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to a method. The method may provide a tile database with multiple tiles that define one or more first component sections for a memory device. The method may define an array of storage elements having a specified memory array width. The method may define one or more second component sections having at least part of a standard cell based tile with standard cells arranged in multiple standard cell rows. The method may generate a memory instance by defining a layout for the memory device with the multiple tiles selected from the tile database based on matching the multiple standard cell rows to the specified memory array width of the array of storage elements.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.