Sensing techniques for a memory cell
US11289147B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2021 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Feb 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/2293
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.