Static random access memory (SRAM) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and SRAM bit cell array circuits
US11289495B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Sep 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.