Initialization sequencing of chiplet I/O channels within a chiplet system
US11294848B1 · kind B1 · utility
3Cited by
0References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2020 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Oct 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/538
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.