Selective accelerated sampling of failure-sensitive memory pages
US11301143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2019 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Jan 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device in a memory system determines sensitivity value of a memory page in the memory system. The processing device assigns the memory page to a sensitivity tier of a plurality of sensitivity tiers based on a corresponding sensitivity value, wherein each sensitivity tier has a corresponding range of sensitivity values. The processing device further determines a targeted scan interval for each sensitivity tier of the plurality of sensitivity tiers and scans a subset of a plurality of memory pages in the memory component, wherein the subset comprises a number of memory pages from each sensitivity tier determined according to the corresponding targeted scan interval of each sensitivity tier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.