Area efficient and high-performance wordline segmented architecture
US11302365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2019 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Sep 26, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array including a plurality of memory cells and a plurality of drivers is disclosed. The plurality of memory cells may be arranged in a plurality of rows and a plurality of columns. Memory cells corresponding to a row of the plurality of rows may be logically grouped into a plurality of memory array segments. The plurality of drivers may be coupled to corresponding first ends of corresponding memory array segments of the plurality of memory array segments. Second ends of the corresponding memory array segments may be coupled to second ends of corresponding adjacent memory array segments of the plurality of memory array segments. The second ends of the corresponding memory array segments and the second ends of corresponding adjacent memory array segments may be coupled to corresponding wordlines of a plurality of wordlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.