Memory device with circuitry to transmit feedback indicative of a phase relationship
US11302368B2 · kind B2 · utility
2Cited by
45References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Nov 19, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship between the control signal and the timing signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.