Composite wafer, semiconductor device and electronic component
US11302579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | May 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.