Interconnects including dual-metal vias
US11302637B2 · kind B2 · utility
0Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Aug 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) structure includes a dielectric layer extending along a first axis to define a length and a second axis orthogonal to the first axis to define a width. A dual-metal via is embedded in the dielectric layer. The dual-metal via includes via sidewalls surrounding a via core. An electrically conductive line extends along the first axis and on an upper surface of the dual-metal via. A side portion of the via core is co-planar with a sidewall of the electrically conductive line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.