High voltage integration for HKMG technology
US11302691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Sep 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
Abstract
The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.