DRAM with selective epitaxial cell transistor

US11302697B2 · kind B2 · utility

Assignee

• Integrated Silicon Solution, (Cayman) Inc. · KY

Inventors

• Andrew J. Walker · Mountain View, US
• Dafna Beery · Palo Alto, US
• Peter Cuevas · Los Gatos, US
• Amitay Levi · Cupertino, US

Key dates

• Filing date: Jan 28, 2020
• Grant date: Apr 12, 2022
• Expiry date: Jan 28, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/485

Abstract

A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer.