Combined SHA2 and SHA3 based XMSS hardware accelerator
US11303429B2 · kind B2 · utility
2Cited by
1References
16Claims
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Key dates
| Filing date | Jun 28, 2019 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Aug 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.