Power semiconductor package having integrated inductor, resistor and capacitor

US11309233B2 · kind B2 · utility

Assignee

• Alpha and Omega Semiconductor (Cayman) Ltd. · KY

Inventors

• Xiaotian Zhang · San Jose, US
• Mary Jane R. Alin · Shanghai, CN
• Bo Chen · Shanghai, CN
• David Brian Oraboni, JR. · San Jose, US
• Long Wang · Cupertino, US
• Jian Yin · Waterloo, CA

Key dates

• Filing date: Feb 25, 2020
• Grant date: Apr 19, 2022
• Expiry date: Mar 28, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19105
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.