Semiconductor structure and method of manufacturing the same
US11315930B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Oct 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/666
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a substrate, a first word line structure, a second word line structure, a third word line structure, and a fourth word line structure. The substrate has an active region surrounded by an isolation structure. The first and second word line structures are disposed in the active region and separated from each other. The third and fourth word line structures are disposed in the isolation structure, and each of the third and the fourth word line structures includes a bottom work-function layer, a middle work-function layer on the bottom work-function layer, and a top work function layer on the work-function middle layer. The middle work-function layer has a work-function that is higher than a work-function of the top work-function layer and a work-function of the bottom work-function layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.