Information redistribution to reduce side channel leakage
US11321460B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2019 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | May 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic circuit includes a data signal input, a computational module, a direct timing modulator and an amplitude and non-direct timing modulator. The data signal input inputs data signals. The computational module includes multiple logic elements interconnected to perform a logic function. The direct timing modulator modulates a propagation time of the input data signals from the data signal input to the computational unit, in accordance with a first set of control signals. The amplitude and non-direct timing modulator modulates the processing time of data signals by the computational module and the amplitude of data signals propagating through the computational module, in accordance with a second set of control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.