Memory system, integrated circuit system, and operation method of memory system
US11322219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Jul 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system may include a memory controller suitable for transmitting write data and a first write ECC corresponding to the write data during a write operation, a first error correction circuit suitable for detecting whether the write data received from the memory controller has an error, using the first write ECC received from the memory controller, and correcting the error when the error is detected, a second ECC generation circuit suitable for generating a second write ECC using the write data received from the memory controller, and generating the second write ECC using the write data whose error has been corrected by the first error correction circuit, when the detection of the error is noticed from the first error correction circuit, and one or more memories suitable for storing the second write ECC and write data corresponding to the second write ECC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.