Clock circuit and method of operating the same
US11323101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2021 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Mar 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.