Chip testing system for testing chips
US11327110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2020 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Sep 16, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A chip testing system includes a central control device, a chip mounting apparatus, a plurality of environment control apparatus, a classification apparatus, and a transferring apparatus. The central control device is configured to control the chip mounting apparatus to dispose a plurality of chips onto a chip testing device. Each of the environment control apparatus includes a plurality of accommodating chambers that are independent from each other. Each of the accommodating chambers is provided with a temperature adjusting device. The central control device is configured to control the transferring apparatus to place the chip testing device into one of the accommodating chambers. When the chip testing device carrying the chips is arranged in the corresponding accommodating chamber, the central control device is configured to control an operation of the corresponding temperature adjusting device, so that the chips are in an environment of a predetermined temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.