Bitcell architecture with buried ground rail
US11328750B1 · kind B1 · utility
5Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2021 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Jan 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are related to a device with a backside power network. The backside power network may have a buried power rail that is coupled to ground. The device may have a read-only memory (ROM) cell that is coupled between at least one bitline and the buried power rail, and the ROM cell may be coupled to ground by way of the buried power rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.