Reduced verify scheme during programming based on spacing between verify levels
US11328780B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2020 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Dec 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and techniques are described for optimizing a program operation in a memory device in which groups of memory cells are programmed from checkpoint states to respective data states. In a first program pass, groups of memory cells are programmed to respective checkpoint states with verify tests. Each checkpoint state is associated with a set of data states. In a second program pass, the memory cells are programmed closer to their assigned data state with a specified number of program pulses. In a third program pass, the memory cells are programmed to their assigned data state by applying program pulses and performing verify tests. The number of checkpoint states and the number of data states associated with each checkpoint state can be optimized based on a spacing between the verify voltages of the data states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.