Semiconductor device having planar transistor and FinFET
US11328958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2020 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Oct 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes first and second transistors and first and second isolation structures. The first transistor includes a raised structure, a first gate structure over the raised structure, and a first source/drain structure over the raised structure and adjacent the first gate structure. The first isolation structure surrounds the raised structure and the first source/drain structure of the first transistor. A bottommost surface of the first source/drain structure is spaced apart from a topmost surface of the first isolation structure. The second transistor includes a fin structure, a second gate structure over the raised structure, and a second source/drain structure over the fin structure. The second isolation structure surrounds a bottom of the fin structure of the second transistor. A bottommost surface of the second source/drain structure is in contact with a topmost surface of the second isolation structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.