Operational modes for reduced power consumption in a memory system
US11335416B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Dec 16, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for operational modes for reduced power consumption in a memory system are described. A memory device may be coupled with a capacitor of a power management integrated circuit (PMIC). The memory device may operate in a first mode where a supply voltage is provided to the memory device from the PMIC. The memory device may operate in a second mode where it is isolated from the PMIC. When isolated, a node of the memory device (e.g., an internal node) may be discharged while the capacitor of the PMIC remains charged. When the memory device resumes operating in the first mode, a supply voltage may be provided to it based on the residual charge of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.