Transistors with back-side contacts to create three dimensional memory and logic

US11335686B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Wilfred Gomes · Portland, US
• Mauro J. Kobrinsky · Portland, US
• Abhishek A. Sharma · Hillsboro, US
• Tahir Ghani · Portland, US
• Doug B. Ingerly · Portland, US
• Rajesh Kumar · Palo Alto, US

Key dates

• Filing date: Oct 31, 2019
• Grant date: May 17, 2022
• Expiry date: Oct 31, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/36

Abstract

Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.