Channel structures for thin-film transistors

US11335789B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Abhishek A. Sharma · Hillsboro, US
• Cory E. Weber · Portland, US
• Van H. Le · Portland, US
• Sean T. Ma · Portland, US

Key dates

• Filing date: Sep 26, 2018
• Grant date: May 17, 2022
• Expiry date: Sep 17, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D99/00

Abstract

Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.