Semiconductor processing system with in-situ electrical bias and methods thereof
US11335792B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Apr 6, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Apr 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.