Apparatus and methods for synchronizing a plurality of double data rate memory ranks
US11340786B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 11, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Nov 11, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared data transfer clock is used among double data rate memory ranks. A memory controller processes incoming memory access commands destined for at least one of a plurality of double data rate memory ranks and determines when a target DDR memory rank is out of synchronization with respect to the shared data transfer clock and a memory clock. In response to determining that the target DDR memory rank is out of synchronization, the memory controller determines whether the non-target DDR memory rank is out-of-synchronization with respect to the shared data transfer clock and the memory clock, and issues a data transfer clock synchronization command to the target DDR memory rank in response to determining that the non-target DDR memory rank is out-of-synchronization with respect to the shared data transfer clock and the memory clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.