Tahsin Askar
19Patents
6h-index
19Co-inventors
63Inventor score
Filing activity: Sep 25, 1998 → Jun 29, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6081864A | Dynamic configuration of a device under test | Physics | 36 | Expired |
| US7924637B2 | Method for training dynamic random access memory (DRAM) controller timing delays | Physics | 22 | Active |
| US6154801A | Verification strategy using external behavior modeling | Physics | 18 | Expired |
| US6760791B1 | Buffer circuit for a peripheral interface circuit in an I/O node of a computer system | Physics | 11 | Expired |
| US6173243A | Memory incoherent verification methodology | Physics | 11 | Expired |
| US7761656B2 | Detection of speculative precharge | Physics | 9 | Active |
| US6996657B1 | Apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system | Physics | 6 | Expired |
| US6725297B1 | Peripheral interface circuit for an I/O node of a computer system | Physics | 6 | Expired |
| US6834314B1 | Method and apparatus for reordering packet transactions within a peripheral interface circuit | Physics | 6 | Expired |
| US6760792B1 | Buffer circuit for rotating outstanding transactions | Physics | 5 | Expired |
| US9122648B2 | Temperature throttling mechanism for DDR3 memory | Physics | 5 | Active |
| US6757755B2 | Peripheral interface circuit for handling graphics responses in an I/O node of a computer system | Physics | 5 | Expired |
| US6823405B1 | Method and apparatus for initiating partial transactions in a peripheral interface circuit for an I/O node of a computer system | Physics | 4 | Expired |
| US8006032B2 | Optimal solution to control data channels | Physics | 3 | Active |
| US8607104B2 | Memory diagnostics system and method with hardware-based read/write patterns | Physics | 3 | Active |
| US6968417B1 | Method and apparatus for reducing latency in a peripheral interface circuit of an I/O node of a computer system | Physics | 1 | Expired |
| US12299297B2 | Memory controller with enhanced low-power state | Physics | 0 | Active |
| US6883045B1 | Apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system | Physics | 0 | Expired |
| US11340786B2 | Apparatus and methods for synchronizing a plurality of double data rate memory ranks | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.