Low-power multi-stage/multi-segment content addressable memory device
US11342022B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Nov 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.