Circuit and method for process and temperature compensated read voltage for non-volatile memory
US11342031B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Aug 28, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Aug 28, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.