Memory apparatus and method of operation using one pulse smart verify
US11342035B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Nov 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells each connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and the strings determines a program lower tail voltage of a distribution of the threshold voltage following a first program pulse. The control circuit calculates a second program voltage of a second program pulse based on the program lower tail voltage and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltage of the memory cells have a desired program lower tail voltage without further program pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.