System and method for objective probing and generation of timing constraints associated with an electronic circuit design
US11347915B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Jun 3, 2021 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Jun 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving an electronic design having a plurality of objects associated therewith. Embodiments may further include allowing, at a graphical user interface, a user to define at least one user-refined filter selected from the group consisting of an instance pin filter, a library cell instance filter, a clock pin filter, and a net filter. Embodiments may also include generating one or more constraints based upon, at least in part, the user-refined filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.