Thin film transistor random access memory
US11348928B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 3, 2021 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Mar 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.