Three-dimensional memory devices and fabricating methods thereof
US11348936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2019 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Apr 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.