Integrated assemblies, and methods of forming integrated assemblies
US11348939B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2019 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Jul 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.