Backside vias in semiconductor device
US11349004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2020 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Oct 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.