Accelerated processing of streams of load-reserve requests
US11354243B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Dec 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing unit for a data processing system includes a processor core that issues memory access requests and a cache memory coupled to the processor core. The cache memory includes a reservation circuit that tracks reservations established by the processor core via load-reserve requests and a plurality of read-claim (RC) state machines for servicing memory access requests of the processor core. The cache memory, responsive to receipt from the processor core of a store-conditional request specifying a store target address, allocates an RC state machine among the plurality of RC state machines to process the store-conditional request and transfers responsibility for tracking a reservation for the store target address from the reservation circuit to the RC state machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.