Conductive via of integrated circuitry, memory array comprising strings of memory cells, method of forming a conductive via of integrated circuitry, and method of forming a memory array comprising strings of memory cells
US11355392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Nov 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalk of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.