Vertical backend transistor with ferroelectric material
US11355505B2 · kind B2 · utility
7Cited by
4References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 29, 2017 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Dec 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and mechanisms to provide a memory array comprising a 1T1C (one transistor and one capacitor) based memory cell. In an embodiment, the memory cell comprises a transistor, fabricated on a backend of a die, and a capacitor which includes a ferroelectric material. The transistor of the 1T1C memory cell is a vertical transistor. In another embodiment, the capacitor is positioned vertically over the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.