Three-dimensional memory device and method
US11355516B2 · kind B2 · utility
8Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Oct 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.