Systems and methods for dual-pulse programming
US11361834B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2020 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Dec 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprising control circuitry configured to apply a first program voltage to a selected word line, wherein a first subset of memory cells of the selected word line, that correspond to a first set of data states, are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to a second subset of memory cells corresponding to a second set of data states. The control circuitry is further configured to cause a first voltage of the selected word line to discharge to a second voltage level corresponding to a second program voltage such that the second program voltage is applied to at least the first subset of memory cells. The control circuitry is further configured to perform a verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.