Diffusion barrier layer for conductive via to decrease contact resistance
US11362035B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2020 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Mar 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive structure is disposed within the first ILD layer. A capping layer continuously extends along a top surface of the lower conductive structure. An upper ILD structure overlies the lower conductive structure. A conductive body is disposed within the upper ILD structure. A bottom surface of the conductive body directly overlies the top surface of the lower conductive structure. A width of the bottom surface of the conductive body is less than a width of the top surface of the lower conductive structure. A diffusion barrier layer is disposed between the conductive body and the upper ILD structure. The diffusion barrier layer is laterally offset from a region disposed directly between the bottom surface of the conductive body and the top surface of the lower conductive structure by a non-zero distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.