Method for the electrical bonding of semiconductor components
US11362061B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 19, 2020 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Sep 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01327
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for electrically bonding a first semiconductor component to a second semiconductor component, both components including arrays of contact areas. In one aspect, prior to bonding, layers of an intermetallic compound are formed on the contact areas of the second component. The roughness of the intermetallic layers is such that the intermetallic layers include cavities suitable for insertion of a solder material in the cavities, under the application of a bonding pressure, when the solder is at a temperature below its melting temperature. The components are aligned and bonded, while the solder material is applied between the two. Bonding takes place at a temperature below the melting temperature of the solder. The bond can be established only by the insertion of the solder into the cavities of the intermetallic layers, and without the formation of a second intermetallic layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.