Select gate gate-induced-drain-leakage enhancement
US11362175B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2021 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Mar 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/696
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of the topmost select gate transistors to strings of memory cells upon application of a voltage to the gates of the topmost select gate transistors. This electric field can be provided by using a dissected plug as a contact to the channel structure of the topmost select gate transistor, where the dissected plug has one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure. The dissected plug can be part of a contact between the data line and the channel structure. Additional devices, systems, and methods are discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.