Managing bin placement for block families of a memory device based on trigger metric values
US11372545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Nov 6, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device of a memory sub-system is configured to select, during a first period of time of a plurality of predetermined periods of time, a first voltage bin of a plurality of voltage bins associated with a memory device, wherein each bin of the plurality of voltage bins is associated with a corresponding set of read level offsets; perform, during a second period of time, a read operation of a block of the memory device, using a first set of read level offsets associated with the first voltage bin; determine a trigger metric associated with the first set of read level offsets; and responsive to determining that the trigger metric fails to satisfy a predefined condition, select a second voltage bin, wherein a second set of read level offsets associated with the second voltage bin is associated with a second trigger metric that satisfies the predefined condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.