Patent · US Active

Data processing engine tile architecture for an integrated circuit

US11372803B2 · kind B2 · utility

0Cited by

37References

19Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Goran H K Bilski · Mölndal, SE
Juan J. Noguera Serra · San Jose, US
Baris Ozgul · Dublin, IE
Jan Langer · Chemnitz, DE
David Clarke · Dublin, IE
Sneha Bhalchandra Date · Santa Clara, US

Key dates

Filing date	Apr 3, 2018
Grant date	Jun 28, 2022
Priority date	—
Expiry date	Jan 27, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F15/8053
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.