Boost schemes for write assist
US11373702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2019 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Oct 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.