Patent · US Active

Device, method and system for providing a stacked arrangement of integrated circuit dies

US11373987B2 · kind B2 · utility

1Cited by

2References

7Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Wilfred Gomes · Portland, US
Mark Bohr · Beaverton, US
Glenn J. Hinton · Portland, US
Rajesh Kumar · Palo Alto, US

Key dates

Filing date	Dec 28, 2017
Grant date	Jun 28, 2022
Priority date	—
Expiry date	Apr 8, 2038

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.