Patent · US Active

Deep trench via for three-dimensional integrated circuit

US11373999B2 · kind B2 · utility

2Cited by

0References

26Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Yih Wang · Portland, US
Rishabh Mehandru · Portland, US
Mauro J. Kobrinsky · Portland, US
Tahir Ghani · Portland, US
Mark Bohr · Beaverton, US
Marni Nabors · Portland, US

Key dates

Filing date	Jun 7, 2018
Grant date	Jun 28, 2022
Priority date	—
Expiry date	Oct 28, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/834
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.